In the prior art there exists various approaches to provide one-time programmable memory cells. The U.S. Pat. No. 6,856,540 B2 for instance discloses a programmable memory cell comprised of a transistor located at the cross point of a column bit line and a row word line. The transistor has its gate formed from the column bit line and its source connected to the row word line. The memory cell is programmed by applying a voltage potential between the column bit line and the row word line to produce a programmed n+ region in the substrate underlying the gate of the transistor.
Arranging a multiplicity of transistors at cross points of column bit lines and row word lines may provide a storage capacity of several kilobytes. However, the arrangement of transistors at cross points of columns and rows requires a respective addressing scheme which forms a respective overhead, which may be disadvantageous for the design of miniaturized memory cells and are not suitable for small memories.